Re: DRAM refresh

From: Gerrit Heitsch <*gerrit_at_laosinh.s.bawue.de*> Date: Thu, 13 Oct 2016 16:39:12 +0200 Message-ID: <5944ea35-9785-aac2-37a3-52a27c52edc3@laosinh.s.bawue.de> · gerrit_at_laosinh.s.bawue.de

On 10/13/2016 07:45 AM, Marko Mäkelä wrote:
> By the way, how long would the DRAM contents survive without refresh?
> Maybe it is possible to find this out on a C16 or plus/4, by 'halting'
> the TED for some time by constantly resetting one of its horizontal
> counters?

That depends on the DRAM... I remember once reading a test where the 
result was that most US made DRAMs stuck pretty close to the spec. 
Meaning they really needed the 128/2ms or 256/4ms while most japanese 
made DRAMs kept the data much longer, some into the second range.

Also, the question is whether TED's refresh counter is coupled to the 
horizontal counter or free running and just getting triggered by the 
horizontal counter.

   Gerrit

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