Re: DRAM refresh

From: Gerrit Heitsch <*gerrit_at_laosinh.s.bawue.de*> Date: Sat, 15 Oct 2016 20:47:59 +0200 Message-ID: <6b52e1c9-b26e-93aa-07d6-1fad2286f5b9@laosinh.s.bawue.de> · gerrit_at_laosinh.s.bawue.de

On 10/15/2016 08:38 PM, Segher Boessenkool wrote:
> On Sat, Oct 15, 2016 at 06:49:45PM +0200, Gerrit Heitsch wrote:
>>>> AFAIR the VIC-II row counter for refresh is free-running.  I'll have
>>>> a look later.
>>>
>>> It is reset at the end of the frame, actually.
>>
>> I wonder why they do that... Making sure that the counter can't get
>> stuck somehow?
>
> Probably.  The VIC-II does not have an external reset signal; instead,
> most blocks rely on being reset some other way, usually from the frame
> timing.  The first frame output can be very, uhh, interesting.  This
> may be another reason why they opted for a separate (from matrix fetch)
> refresh, btw.

The same applies to TED by the way, no RESET input. It either comes up 
properly at power on or you're in trouble.

> Another reason to reset the refresh counter every frame is to make sure
> all frames are alike, which might help validation etc.

As long as they meet the refresh specs it doesn't matter.

  Gerrit

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