On 12/29/2016 07:45 PM, David Wood wrote: > Is it possible to detect a delay without a clock? I suppose this is > also not infallible since accelerators could trigger it. Of course, you can set a monoflop with the first access and if the next access happens outside the time where the monoflop remains set, it's not a RESET vector pull. But that needs finetuning since tolerances in the RC-circuit will influence the time. Take a look at the 74LS123 for details. Gerrit > > On Thu, Dec 29, 2016 at 1:28 PM, Michał Pleban <lists@michau.name > <mailto:lists@michau.name>> wrote: > > Hello! > > silverdr@wfmh.org.pl <mailto:silverdr@wfmh.org.pl> wrote: > > > If we want to keep compatibility - I am afraid the answer is "yes". A simple example: a program uses the RAM area under KERNAL as a temporary storage and reads from the consecutive addresses there. I know for a fact that such programs exist. So you would need to monitor the configuration bits or the _CS or ... The next example is copying KERNAL from ROM to RAM - lots of programs to this in order to modify a few things in the KERNAL. Here monitoring the _CS won't help as the program reads from ROM locations and you know what happens when you don't differentiate between the _RST induced reads and the same done by the program. > > This is a valid point. As Gerrit said, you cannot distinguish the CPU > reading the reset vector during the RESET, and the CPU reading the reset > vector as a part of some user code. > > So it looks like the only thing you can do is to hook some more control > signals from SID or VIC. > > Regards, > Michau. > > > > > Message was sent through the cbm-hackers mailing list > > Message was sent through the cbm-hackers mailing listReceived on 2016-12-29 19:01:07
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