Hi Ruud! On Thu, Dec 28, 2017 at 3:18 PM, Baltissen, GJPAA (Ruud) <ruud.baltissen@apg.nl> wrote: > Hallo Frank, > > >>I haven't seen a schematic where this phi2 latching action is actually exploited, everyone's using a simple '138 to decode all the CS and phi2 into a single /CE for the EPROM > > Ehhh, don't you mean a multi-input AND gate? hm not really. CS1, CS2 are active high, CS3 to CS5 and PHI2 are active low (at least on all 6540s on a 2001), so you can't get away with an AND gate. You would need more than one gate. On my 6550 replacement board I've used 4 gates but only because they were easier to hide on the original 6550 footprint than a single '138. > > >> then it means that the address bus is stable during the high phi2 phase anyway. > > In case of a 6502 it is. And it has to bee otherwise a 6522 won't work correctly. That is the main reason a 6522 won't work with in a C64 = > 6510 because the address bus is not stable at the rising edge of PHI2. There is even a risk that the VIC-II is still busy for quite some > nanoseconds as I found out 25 years ago (wow, already that long ago?) with my hard disk drive project for the C64, http://baltissen.org > /newhtm/c64ide.htm, read the details there. ok, so that's why a 2716 with some glue logic only and no latches works fine. > > I don't have any idea why the 6540 needs the latch. An EPROM doesn't need one. it probably doesn't *need* a latch, they thought it would be useful in some other architectures, before deciding it would be cheaper to add more glue logic and use standard RAM/ROMs. If the 6540 latches addresses internally on rising edge of PHI2 it means it can't easily be read on a standard programmer. Frank Message was sent through the cbm-hackers mailing listReceived on 2017-12-28 15:00:02
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