Re: testing 6550s outside a 6502 bus

On Thu, Jan 4, 2018 at 7:09 PM, Gerrit Heitsch
<gerrit@laosinh.s.bawue.de> wrote:
> On 01/04/2018 06:56 PM, Francesco Messineo wrote:
>>
>> Hi all,
>> as I'm repairing a 2001 320008 assy, I'm trying to test the 6550s and
>> 6540s on a microcontroller board that I've made.
>> I would use a real 6502, but I've only one spare left, so that's not
>> an option :)
>>
>> It seems that the 6550 latches the selects, address and R/W line (for
>> example lowering R/W after PHI2 L->H always results in a read cycle)
>> on the rising edge of PHI2, but still I can't make a correct read or
>> write cycle.
>
>
> How much time before the rising edge of PHI2 did you set up the address
> lines? There might be a minimum (and maybe maximum...) setup time for the
> address lines before PHI2 can go high.

I thought that, I'm now on 200 ns setup time (huge). I doubt it's
really so high on a real 6502 bus.
Most of the 6502 compatible device live with 50 to 80 ns setup time.
Also going under 100 ns didn't help anyway.
I'm really about to use a timer to make a real phi2 and try to
synchronize with it all the read/write cycles with 1 MHz compatible
timings.
Out of desperation of course.

Frank

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