Hallo Frank,
> BTW, how you plan latch D8..15 into PRA?
This is taken from a document I have of the VIC-20. The document self came
from FUNET in the first week I visited the WEB (1990 ???):
ACR : AUXILIARY CONTROL REGISTER
___ ___ ___ ___ ___ ___ ___ ___
| | | | | | | | |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
T1 control |___|___|___|___|___|___|___|___|
0 = Disable PB7 output ___________________| | | |_______| | |
1 = Enable PB7 output | | | | |
| | | | |
T1 control | | | | |
0 = one-shot mode ____________________________| | | | |
1 = free-running mode | | | |
| | | |
T2 control | | | |
0 = decrement by 6502 system clock _____________| | | |
1 = decrement by input pulses on PB6. | | |
| | |
Used for controlling Shift-register ______________________| | |
(treated separately) | |
| |
Port B input latch ______________________________________________| |
0 = disable latch, 1 = enable latch |
|
Port A input latch ___________________________________________________|
0 = disable latch, 1 = enable latch
The only feature of the ACR that hasn't been mentioned yet is the latching
mentioned above for bit 0 and bit 1. There are two variations of input
behaviour for Port A and Port B depending on whether latching is enabled or
disabled. If latching is disabled, the level present at an input (i.e. the
relevant PB or PA pin) is read into IRB or IRA respecitively. If the latch
is enabled, the level read into IRB/A is that which existed after the 'last
active transition' arriving on CB1/CA1 (when a pulse of the correct
phasing and shape hit CB1/CA1 input). In other words, if the conditions
existing now are required, then latch must be in the disabled condition. We
only enable latching if we require CB1/CA1 to act as a data-valid signal
and we wish to ignore levels arriving after the latching.
==========================================================================
The above latching is used in the 1541, see my site: 1540.gif Better use
the complete SCH of a 1540. Notice that the signal that leads to CA1 also
goes to the SO-input of the 6502.
In the case of reading a 16-bits data bus, CA1 should be connected to the
output of an AND-gate what on its turn ANDs IORD and MEMRD. The result is
that at the and of a read-cycle the data is latched inside the 6522. The
CPU has read D0..8 and now can read the stored D8..15.
If you still have questions, be my guest and I'll be happy to answer them.
Groetjes, Ruud
http://Ruud.C64.org/
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