Hallo allemaal, I'm afraid I have some said news. It seems we only can DMA at about 1 MHz ( My research revealed this: The 8237 runs at 4 MHz. The shortest possible transfer needs two cycles = 250 ns = one halve in 2 Mhz mode. Assume we want to write to the C64. The MEMW line becomes active (L) max. 190 ns after the CLK for the 8237 becomes (H). MEMW becomes inactive again 130 ns. after the next CLK becomes (H). This means it only lasts active (L) for 190 ns. And that is not enough to cover the AFAIK min. 250 ns. we need. The second problem is the timing. The weird numbers of "max 190/130 ns." alone give me headache enouch. I have no idea what cycle of the 4 MHz clock is seen as the first one. The READY input enables on to synchronize the 8237 with CLK2. But to make sure the operation covers the complete upper halve of CLK2, an upgoing edge must be detected first. This means we certainly end up spending 3 cycles per transfer meaning we can forget a speed of 2 MHz. For the moment I don't see any problem in letting the C128 running in 2 MHz mode anyway. As the ISA-bus is not hindered by CLK2, a M2M-transfer between a C128 and ISA will transfer at roughly 1.5 MB/sec. ISA <-> ISA transfers are not hindered at all, AFAI see. A second opinion is welcome, please. Groetjes, Ruud http://Ruud.C64.org - This message was sent through the cbm-hackers mailing list. To unsubscribe: echo unsubscribe | mail cbm-hackers-request@dot.tml.hut.fi.
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