>>>>> "MvB" == Martijn van Buul <martijnb@stack.nl> writes:
RB> Maybe a strange, even weird question but would a 1 or 2 MHz
RB> interrupt be possible on a fast PC?
CP> At the highest interrupt level it would probably be possible, but
CP> it would seriously hurt performance. It wouldn't be very useful.
MvB> I wonder if it *is* possible, considering things like cache loss,
MvB> busted pipelines, that kind of yadda-yadda.
Agreed. On a 500 MHz CPU you'll get a maximum of about 500 instruc-
tions per interrrupt, and the the interrupt latency including context
switch is usually somewhere between 200-300 cycles, iirc.
--
___ . . . . . + . . o
_|___|_ + . + . + . . Per Olofsson, konstnär
o-o . . . o + MagerValp@cling.gu.se
- + + . http://www.cling.gu.se/~cl3polof/
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