what you CAN do is the sit-and-wait method. :) Instead of relying on an interrupt (and therefore a context change) for timing, make an infinite loop poll whatever you're timing from (be it a timer at 1mhz, whatever), and when it clears, continue. Add nauseum. On Mon, 7 May 101 g.baltissen@hccnet.nl wrote: > Hallo Per, > > > Agreed. On a 500 MHz CPU you'll get a maximum of about 500 instruc- > > tions per interrrupt, and the the interrupt latency including context > > switch is usually somewhere between 200-300 cycles, iirc. > > I was thinking about a 486-66. Seems we can forget the idea for the moment. > But within 5 years these 500-machines will be available for pennies, I hope > :) > > Groetjes, Ruud > > http://Ruud.C64.org/ > > > > - > This message was sent through the cbm-hackers mailing list. > To unsubscribe: echo unsubscribe | mail cbm-hackers-request@dot.tml.hut.fi. > - This message was sent through the cbm-hackers mailing list. To unsubscribe: echo unsubscribe | mail cbm-hackers-request@dot.tml.hut.fi.
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