Hi Marko,
"Marko Mäkelä" wrote:
> A minor correction that may make a major difference when the timing is
> tight: the interrupt cannot occur immediately after the instruction that
> cleared the Interrupt flag (RTI, CLI or PLP), but after the following
> instruction. Due to the instruction pipeline in the 6502, the interrupt
> condition must be enabled 2 cycles before the end of the currently
> executing instruction in order for the interrupt to be taken. I haven't
> seen this documented anywhere, but I've measured this on the C64.
I believe to remember that the 65xx software (or hardware?) handbook (or how
it is called) by MOS Technologies (that is shipped with the KIM1, for
example) mentions this, as it mentions the exact timing of the interrupt (or
RESET) procedure. Unfortunately, my copy of this book is far away, so I
cannot check it...
Spiro.
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