On Tue, 21 Aug 2001, David Wood wrote:
> Have a look at
> http://starbase.globalpc.net/~jbevren/./rec.txt
> to see what I've found during some research into the idea of making an 16M
> reu controller. Of course, its just a framework of information, but it
> should help anyone wanting to design the REC.
The Lattice ispLSI 2064VE has 64 programmable I/O pins and 64 latches (8
bytes of memory). The I/O pin count is not a problem: there are enough
pins for connecting 16 MB of SDRAM and 8 MB of Flash ROM.
But the memory is a little tight. In the document, you give an estimate
of eleven 8-bit latches. The writeable registers $df01-$df0a require ten
8-bit latches, but you could leave some unused bits out. And then you
need one or two latches for the swap operation.
I was thinking of a somewhat simplified design. First of all, I'd omit
the "interrupt after transfer" feature, since it is pretty useless. When
it is enabled, the CPU will be interrupted right after the write command
(to $df01 or $ff00) that initiated the transfer. Also, I don't know if
the verify and swap commands are worth the trouble. I don't see how you
could use an 8-input and gate in the verify operation. Of course there
are bigger logic chips than the 2064. Maybe the 2096 would be big enough
for implementing also an Action Replay like device in addition to a fully
backwards compatible REU clone.
Marko
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