> Does anyone (Rainer?) have experience in designs like this?
Concerning the serial method I have to admit: no. Although according to
the data sheet this is far the easiest method since the FPGA provides the
necessary signals by itself, we've used only the parport boot method so
far where an involved microcontroller/processor boots the FPGA from data
stored in the uC's ROM.
> If the total cost of parts is less than $20 or $30, I think that it
> would be feasible to build a 16 MB REU clone (possibly including some
> Flash ROM, such as the Am29LV640 that provides 8 megabytes).
Now, how about a power-fault detection which automatically saves the DRAM
content to FlashROM when the machine is powered off; similarly the
contents will be restored on power-on.
Just dreaming :)
> When all parts are in-system programmable, the first prototypes could
> omit most of the planned features, and the VHDL code could be written
> as a joint project. The entire design would be open-source, of
> course.
I have already built some REU concept a year ago or something, but I
recognized that I internally needed to double dotclock for proper
operation of the internal state machine (allow swap operation and DRAM
refresh). There's some Xilinx app note about generating a clock doubler
through some delay/xor logic but it also says that one should only use it
when everything else fails...
Do you circumvent that by some clever design trick I was too blind to see?
Working *together* on *free* VHDL models of the various custom chips (and
the CPU) is something I'd highly appreciate. I don't want to know how many
of us (including me) have already started to code their very own models of
6502/10, 6526 and 6567/9 and got stuck at various stages just due to a
lack of time or lost interest.
Rainer
--
Rainer Buchty, LRR, Technical University of Munich
Phone: +49 89 289-28401, Fax +49 89 289-28232, Room S3240
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