> Sure, that would be enough. But how do you achieve the biphase clocking
> based on dotclock? The only logic chip I know which is capable of doing
> biphase clocking by default is the Mach5 family from Vantis/Lattice, all
> other logic chips I know need some delayed arithmetics like the one you
> described to double a clock. That will result in a phase shift of the
> double speed clock (somewhere between 5 and 20ns) but I don't think we'll
> run into problems when dealing with 8MHz max.
Right, you'd have to abandon the global clock and generate your own
(well, you'd presumably use the global clock in the generation)
And probably CPLD delays wouldn't be much of a problem at dot clock
speeds, also I would assume you could arrange for similar delays,
so that skewing could be minimized.
For myself, I'm planning on doing it discretely (DRAM/DMA controller,
not
the REC) at least initially, and delays are likely to be significant.
bogax
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