> I am no VHDL guru.
Neither am I...
Since I have written that just "dryly" (currently I'm mot able to check it
since I'm offroad for 2 months) during some moments of bored^w
leisure time while slowly migrating from MESZ to EST - so I'm quite
sure there are some bugs in (such as the BA dupe).
I decided to release it anyway instead of letting it rot on my notebook's
HD so that someone who is more familiar with C64 DMA-transfer and/or DRAM
control could take over or at least hand in some corrections.
> You start by making a component instantiation of an entity you
> haven't defined yet.
That's not the problem. More problematic would be that I forgot to put the
component description into a package... So the component/end component
should be enclosed in package/end package.
> Xilinx at least, wants rising_edge(), falling_edge() (not rising'edge(),
> falling'edge() )
Depends on the tool. Synopsys wants it that way - and that's the one I
have access to frome time to time.
> I think you've got too many elseif's in the "DMA transfer" (?) ie
>
> if rst='0' then
> elsif rising'edge(dotclk) then
> elsif falling'edge(dotclk) then
No, why? Some actions happen with the rising edge, others with the falling
edge. Remember the DRAM discussion we had here some time ago.
Basically, I'm doing all addressing stuff and data fetching during 0->1
and the DRAM controlling during 1->0 to make everything fit into 8
dotclock cycles.
Nothing forbids you to use both edges - unless you don't use them on the
same storage element (the only logic chips supporting that feature I can
remember is the MACH5 CPLD series from Vantis/Lattice).
> I don't think there's any such thing as too many comments.
Usually I'd agree - but I think the signal names are pretty much
self-explaining if you are familiar with the REC registers. Also every
state on the used state machines has a short description.
Regards,
Rainer
--
Rainer Buchty, LRR, Technical University of Munich
Phone: +49 89 289-28401, Fax +49 89 289-28232, Room S3240
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