>Yes and no. When the I/O area at $dxxx is accessed in fast mode, the
>VIC-IIe delays the CPU clock signal if the access would have taken place
>in the "wrong" cycle half (the one that would be assigned to the VIC-IIe
>in slow mode).
I thought it was the MMU that had the IOACC? pin and this controlled the
Stretching of the clock cycle (may I have it wrong). The C65 doesn't have
such a feature as the only chip not capable of running at full speed was the
PLEASE TAKE NOTE:
The contents of this email (including any attachments) may be
privileged and confidential. Any unauthorised use of the contents
is expressly prohibited. If you have received this email in error,
please advise us immediately (you can contact us by telephone
on +61 8 9441 2311 by reverse charge) and then permanently
delete this email together with any attachments. We appreciate
your co-operation.
Whilst Orbital endeavours to take reasonable care to ensure
that this email and any attachments are free from viruses or other
defects, Orbital does not represent or warrant that such is explicitly
the case
(C) 2000: Orbital Engine Company (Australia) PTY LTD and its
affiliates
Message was sent through the cbm-hackers mailing list
Archive generated by hypermail 2.1.1.