Hallo allemaal,
Not being able to work on my PC as you could read in my last email, I had to
turn to the hardware. Lately I was asked to use my 6502->65816 module (see
http://home.hccnet.nl/g.baltissen/02to816.htm) for a demonstartion. So I
replaced the 6502 of one of my VIC20's with the module. But opening the case
and showing that there is a 65816 instead of a 6502 on the board is not that
spectacular.
Lately I received an enormous PC-tower for free. I also had some Kaypro
botherbords laying around. These boards only contain the ISA-slots, the
keyboard connector and a RTC. The idea rose to combine everything: a VIC20
able to use PC-cards :)
So I added a 74ALS573 to the VIC20 to generate A16..23. I used a 74LS688,
8-bit comperator, to find out when the first 64 KB segment was addressed.
Next thing was bind this signal into the original design.
UC5, a 138, generates the BLKx signals. I only had to connect one of its
negative enable inputs to the signal.
UC6, another 138, generates the I/O signals in the $9xxx-area. I thought to
be smart and used the BLK4 to enable UC6 instead of the orignal A13. The
VIC20 started but..... no cursor. This puzzled me. The only difference
between both IC's is that UC5 is enabled by CLK2 as well. Connecting BLK4 to
UC6 simply means IMHO that all outputsignals are limited to the time CLK2 =
(H).
QUESTION: has anybody an idea for this behaviour ????
I added an OR-gate to the VIC20 and OR-ed A13 with the segment-signal and
fed the result to UC6. Everything worked out fine.
I AND-ed some BLKx- and RAMx-signals and fed the result to a 32 KB-SRAM. Now
I had 28 KB free RAM.
I fed CLK1 to the enable input of a 74LS239, I/O2 to the A-input and R/W to
the B-input. The four outputs presented the four PC read/write-lines, IORD,
IOWR, MEMR and MEMW.
Then visit arrived and called an end to this fun :( Next time more.
___
/ __|__
/ / |_/ Groetjes, Ruud
\ \__|_\
\___| http://Ruud.C64.org
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