From: Spiro Trikaliotis (trik-news_at_gmx.de)
Date: 2002-04-18 08:01:03
Hello,
"Gideon Zweijtzer" <gideonz@dds.nl> wrote:
> I once made a simple 'logic analyzer' that monitors 16 pins and runs at
> maximum of 40 or 50 MHz, so you have 25 or 20 ns resolution. What I did was
> checking for changes of the signal levels and only storing the changes
> together with a 16-bit timestamp, using a non-linear timer (the longer it
That's exactly what I did with the PC, except that I used a linear timer
and did not use any external logic. This analyzer is even mentioned in my
diploma thesis.
A little bit OT, but someone here might have an answer, and as it might
help in analyzing CBM hardware: ;)
Does anyone know what is the (most) limitating factor when using the PC's
parallel port? Is it the usage of I/O address space, or the usage of the
ISA bus? I could obtain a PCI card for testing, but I don't want to spend
so much money (these are really expensive!) if I don't know if this makes
a significant change.
I know that the CPU spends much wait states when using I/O address space,
as it does when using something on the (internal) ISA bus. Which one is
more limiting? Does anyone know if the parallel ports on external PCI cards
use I/O or memory address space? I did not find any specifications on this.
Anyone?
Thanks in advance,
Spiro.
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