From: Oliver Achten (achten_at_gmx.de)
Date: 2003-08-20 17:13:32
Hallo Ruud!
> > $000000 - $0fffff : 1MB Ram with standard memory mapping (C64
> > i/o space), i.e. 16 virtual C64s
>
> I had the same idea but rejected it. But I later found out there was a
> flaw
> in the reason. I still have some thoughts about it. For example: you still
> need some I/O to tell the VIC where to find it data. Where do you locate
> this I/O?
If a new value is written to the 65816 banking register, the VIC memory is
going to be in the same 64k memory segment like the 65816 CPU, so it will see
the same data. The colour ram would also be switched into a new bank (for 16
virtual C64s well have 16K colour ram, also connected to A16-A19).
> > Memory is slow ram due to extra cycles needed by the VIC.
>
> Like replacing the 4164's by 41256's? Thus no fast SRAM? (if I understand
> correctly)
> Pro: simplifies the design (no addressline latches needed)
> Con: The virtual C64's (VC64) will only run at 1 MHz.
>
> Hmmmm, nein, sorry, don't like that.
I´m afraid you misundertsood me a little bit... (no wonder, because i messed
up with the description a little bit) :-)
Slow Ram: Lets say we take the 7.8Mhz dot clock as the 65816 clock. Then
we´ll have the following timing scheme
vc = vic cycle, cx=cpu cycle
vcvcvcvcc0c1c2c3vcvcvcvcc0c1c2c3vcvcvcvcc0c1c2c3
CPU can only use half of the cycles because of the VIC, making it run at
3.9Mhz
Fast Ram: No VIC, so the cpu owns all 7.8Mhz cycles for itself
c0c1c2c3c4c5c6c7c0c1c2c3c4c5c6c7c0c1c2c3c4c5c6c7
> What about any comments/objections against piling all VC64's up in the
> first
> 64 KB segment?
Because it will take a little bit more hardware to do it.... Damn it,
perhaps i should really go the CPLD way... but it will delay the project. On the
other hand, now that the memory map takes shape, there are some features which
would be very cool, like doing Amiga-like autoconfig stuff etc...
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