ncoplin_at_orbeng.com
Date: 2004-02-10 02:58:22
Hi All,
>> Hmm, what is the RDY input then? Couldn't it be used for implementing
>Wasn't the problem with RDY that it needs up to 3 cycles to be
>acknowledged, i.e. that write cycles can't be interrupted? Clock
>stretching, in term, would work "just in time".
I think that may have been the case with a 6510, but I think that it is a
little different in the 65816 acting almost as a "HALT". From a document off
the net:
=========================================
A low input logic level will halt the microprocessor in its current state
(note that when in the Emulation mode, the G65SC802 stops only during a read
cycle).Returning RDY to the active high state allows the microprocessor to
continue following the next Phase 2 In Clock negative transition.
=========================================
Does everyone else read it the same way?
- Nick
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