From: Rainer Buchty (buchty_at_cs.tum.edu)
Date: 2004-02-10 18:23:33
> Those three cycles are needed because the VIC hasn't any idea what the CPU
> is doing and therefor MUST insert them in case a IRQ is going on.
AFAIK, those three cycles were dictated by the NMOS 6502 which couldn't be
interrupted during write as Andre also pointed out. Later versions like
the 65C02 and its descendants had this corrected.
So in my understanding it works the other way round, i.e. the VIC just has
to assert RDY 3 cycles in advance to be sure it gets the bus when needed,
even if that means that the 6502 waists 3 cycles because it was caught in
a read, not write access.
Rainer
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