From: Jim Brain (brain_at_jbrain.com)
Date: 2004-11-01 15:34:25
Jim Brain wrote:
>
>>> An AVR clocked at 8Mhz should be suitable for jitterless operation
>>> if I'm right...
>>
>>
>>
>> It is, if that is ALL you are doing, or if you can accomplish what
>> you need in the 256 "wait" cycles, but that's not always possible.
>
>
> As an update, I decided to try this. Instead of having both sides of
> the interface handles by different timer IRQs, I combined them, as the
> transfer of 1 byte of data from the originating system is clocks by a
> 20uS clock, which is 160uS/byte. Thus, when I see the falling edge, I
> transfer a byte. The transfer and the parse of the incoming byte is
> taken care of before the charge cycle starts, so the jitter I was
> seeing went completely away.
>
> However, even with no jitter, the LSB still fluctuates. It even
> fluctuates when I comment out all the code except the POT emulation
> code (and set the POTs to 127). So, the SID must not be capable of
> 1LSB resolution. Makes sense, as they were just paddles, who cares
> about the LSB?
>
> Jim
>
I forgot to thank Levente for the idea. Very good idea.
And, as a further update, the SID is not at fault for the jitter, at
least I can't blame it. It's still my code.
I am familiarizing myself with this new scope I bought, and I was able
to zoom in on the leading edges of the waveform. I noticed a 300nS
jitter in catching the SID clamping action, and I noticed a 700nS jitter
in the compare match (when the line goes high). Since my trigger code
is deterministic (the first thing done in the ISR is to bring the line
low), I can only assume that if the AVR is fetching a jmp or branch
instruction when the IRQ happens, the CPU completes all opcodes in the
pipeline before servicing the IRQ. I think the AVR has a 4 stage
pipeline, so that would explain the 3 cycle jitter, and then the 7 cycle
jitter at the match point would be the accumulation of 2 such events.
I have no other interrupts happening in this code (now that I
synchronized the reading of data and the emulation of the POT line).
The delta on SID readings seems to indicate 1/2LSB precision (127
bounces between 127 and 128, for example), which I think is considered
1/2 LSB
In any event, I think possible uses for this code will cope fine with
the error margin, and I have no desire to rewrite for the SX just to get
rid of it. The SX is not offered in as small a package, I'd need a
resonator for the SX to get the high speeds, and something about using a
50MHz CPU to power the joystick port just seems wrong.
Jim
--
Jim Brain, Brain Innovations
brain@jbrain.com http://www.jbrain.com
Dabbling in WWW, Embedded Systems, Old CBM computers, and Good Times!
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