Re: TED badlines, how do they work?

> That would work and I imagine the designers of TED were building on  
> the experience gained from VIC-II. A 2MHz capable on die RAM should  
> be possible.

Sure, given that many things (on both the TED and VIC-II) run at  
8MHz, that
is eminently possible.  The only issue is that faster RAM needs more  
space
and power (needs bigger FETs), but 2MHz should be doable just fine.

> After all, the 656x-VIC-II still needed +12V for parts of the chip  
> (video output drivers?) where TED managed the same with a single  
> +5V supply (and produced more colors).

The power supply for the (analog) output stages, yeah.  8565 uses 5V  
as well,
I'm not sure why the 6569 needed 12V.

More colours is a red herring: the VIC-II has 3 bits of luminance  
already
(which select three different resistance parallel pulldowns to  
ground, it's
not really linear).  You just cannot select chroma and luminance  
separately,
as you can on TED.

>> It's hard to tell, but the TED is only about half the size of the  
>> VIC-II
>> as far as I can tell. About a third or a quarter of that real estate
>> is taken by the sound and timer logic (again, hard to see for sure).
>
> The problem is that the die on the photo is labeled '7360R1' which  
> would make it a HMOS-I TED which should use smaller structures than  
> an NMOS VIC-II (656x). And I forgot about the timers, that would  
> account for some extra space.

"Size" as in "number of FETs", not "area" :-)

The 6569 and 8565 look almost exactly the same, even though they  
supposedly
are quite different scale.

>> Need better pics :-)
>
> I agree... But all the TEDs I own are still working so I'm  
> reluctant to give one up unless really no one has a broken one that  
> can be send to the guys at visual6502...

I thought 90% or so of all those chips were broken by now?  :-P

> Too bad the chip designers at MOS weren't able to use the trick  
> Sinclair implemented in the ULA for the ZX spectrum. There the  
> display byte and the attribute byte were fetched in a single RAS  
> cycle using a page mode access, saving bus time. Needed some tricky  
> arrangement of the address bits on the DRAM to make this possible.  
> It might have eliminated the badlines.

If you look at it the other way around, without badlines there are many
wasted memory cycles.

If they really wanted to improve things, they should have made RDY work
on 6502 write cycles as well (it was designed only for slow (EP)ROM, but
it would be quite useful for writes as well, and it's not so hard to
implement as far as I can see; well harder than AEC, but :-) )


Segher


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