Re: TED badlines, how do they work?

On 09/03/2011 04:37 PM, Segher Boessenkool wrote:
>> After all, the 656x-VIC-II still needed +12V for parts of the chip
>> (video output drivers?) where TED managed the same with a single +5V
>> supply (and produced more colors).
>
> The power supply for the (analog) output stages, yeah. 8565 uses 5V as
> well, I'm not sure why the 6569 needed 12V.

No idea either... But I have a C64 with a 6569R3 (in ceramic :)) where 
the +12V supply was broken. Due to a dead capacitor the VIC only got 
+8V. I still got a picture, but the colors were pale and went completly 
away when the chip warmed up, giving a pure B/W picture. Otherwise the 
system was working fine. Replacing the dead capacitor restored +12V and 
fixed the color issue.



> The 6569 and 8565 look almost exactly the same, even though they supposedly
> are quite different scale.

How do they compare in die size? Otherwise I wouldn't expect many 
changes, after all HMOS is still an NMOS process. Still looks like it 
took MOS 2 Revisions of the 8565 to get it right after the migration to 
HMOS.

Same for TED, the prototype board that was discussed here some time ago 
had a 7360R4A which suggests to me that the 8360R2 doesn't mean '2nd TED 
revision' but '2nd revision of TED in HMOS-II' with an unknown number of 
revisions of the 7360 before.


>>> Need better pics :-)
>>
>> I agree... But all the TEDs I own are still working so I'm reluctant
>> to give one up unless really no one has a broken one that can be send
>> to the guys at visual6502...
>
> I thought 90% or so of all those chips were broken by now? :-P

Not the ones I have... I did have a broken 8501R1 CPU and that got sent 
to visual6502, hoping to see die shots soon... The other 8501 and TED I 
use now and then have heatsinks on them.


>> Too bad the chip designers at MOS weren't able to use the trick
>> Sinclair implemented in the ULA for the ZX spectrum. There the display
>> byte and the attribute byte were fetched in a single RAS cycle using a
>> page mode access, saving bus time. Needed some tricky arrangement of
>> the address bits on the DRAM to make this possible. It might have
>> eliminated the badlines.
>
> If you look at it the other way around, without badlines there are many
> wasted memory cycles.

Hm? A badline means that the CPU is stopped. If there was no badline it 
would run and do more or less useful stuff. My assumption was that by 
using a page mode access to grab data and attributes in one RAS cycle 
the video logic never needs to halt the CPU.

On the other hand, the ULA in the spectrum used a single hardwired 
timing, there were no different video modes and no text mode at all 
(hi-res only!). Maybe it was considered too difficult to make it work on 
the VIC-II.

  Gerrit



       Message was sent through the cbm-hackers mailing list