Re: TED badlines, how do they work?

On 09/04/2011 08:32 AM, Segher Boessenkool wrote:
>>>> After all, the 656x-VIC-II still needed +12V for parts of the chip
>>>> (video output drivers?) where TED managed the same with a single +5V
>>>> supply (and produced more colors).
>>>
>>> The power supply for the (analog) output stages, yeah. 8565 uses 5V as
>>> well, I'm not sure why the 6569 needed 12V.
>>
>> No idea either... But I have a C64 with a 6569R3 (in ceramic :)) where
>> the +12V supply was broken. Due to a dead capacitor the VIC only got
>> +8V. I still got a picture, but the colors were pale and went
>> completly away when the chip warmed up, giving a pure B/W picture.
>> Otherwise the system was working fine. Replacing the dead capacitor
>> restored +12V and fixed the color issue.
>
> Would be interesting to know whether amplifying the output would have
> helped as well :-)

LUMA was OK and didn't change after fixing the +12V supply. Just for fun 
I measured power consumption on +12V for the 6569R5 (4786 15) on my 
testboard. It draws 34-35 mA on +12V alone.


> They added some test pads and did some minor cleanups to the
> routing/layout.
> Perhaps the analog stuff is dimensioned differently as well, I haven't
> looked
> into it.

probably, after all, the 6569 needed +12V for something and the input is 
very close to the analog output drivers. The 8565 does the same with 
+5V. That does suggest some changes in that area.



>> Same for TED, the prototype board that was discussed here some time
>> ago had a 7360R4A which suggests to me that the 8360R2 doesn't mean
>> '2nd TED revision' but '2nd revision of TED in HMOS-II' with an
>> unknown number of revisions of the 7360 before.
>
> Yeah same here. It means R2 of 8360, which has nothing to do with 7360 :-)

It gets a bit confusing with the 7501/8501. Both exist in R1 which makes 
it easy to assume that they are the same... There is a 8501R4 though.


> The VIC-II was originally designed for SRAM, not DRAM; it was obviously
> not considered at all to do tricky things with RAS/CAS timing ;-)

If the VIC was originally designed for SRAM then I wonder why they 
implemented this convoluted address bus (some bits multiplexed, some 
not) and didn't implement it more straigthforward as they did with TED 
which supplies normal addresses and uses the multiplexers as the CPU does.

  Gerrit


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