Re: TED badlines, how do they work?

>>> After all, the 656x-VIC-II still needed +12V for parts of the chip
>>> (video output drivers?) where TED managed the same with a single +5V
>>> supply (and produced more colors).
>>
>> The power supply for the (analog) output stages, yeah. 8565 uses  
>> 5V as
>> well, I'm not sure why the 6569 needed 12V.
>
> No idea either... But I have a C64 with a 6569R3 (in ceramic :))  
> where the +12V supply was broken. Due to a dead capacitor the VIC  
> only got +8V. I still got a picture, but the colors were pale and  
> went completly away when the chip warmed up, giving a pure B/W  
> picture. Otherwise the system was working fine. Replacing the dead  
> capacitor restored +12V and fixed the color issue.

Would be interesting to know whether amplifying the output would have  
helped
as well :-)

>> The 6569 and 8565 look almost exactly the same, even though they  
>> supposedly
>> are quite different scale.
>
> How do they compare in die size?

Dunno.  On the 8565, minimum gate length seems to be 3um and most  
metal tracks
are 6um or so, and the die size is 5.4mm x 4.8mm if I did the  
arithmetic right.
I have no scale reference with the 6569 picture.

> Otherwise I wouldn't expect many changes, after all HMOS is still  
> an NMOS process. Still looks like it took MOS 2 Revisions of the  
> 8565 to get it right after the migration to HMOS.

They added some test pads and did some minor cleanups to the routing/ 
layout.
Perhaps the analog stuff is dimensioned differently as well, I  
haven't looked
into it.

And of course it has that back bias thing.  That's quite a big change.

"Getting it right" can mean so many things, fixes for yield, etc.

> Same for TED, the prototype board that was discussed here some time  
> ago had a 7360R4A which suggests to me that the 8360R2 doesn't mean  
> '2nd TED revision' but '2nd revision of TED in HMOS-II' with an  
> unknown number of revisions of the 7360 before.

Yeah same here.  It means R2 of 8360, which has nothing to do with  
7360 :-)

>>> Too bad the chip designers at MOS weren't able to use the trick
>>> Sinclair implemented in the ULA for the ZX spectrum. There the  
>>> display
>>> byte and the attribute byte were fetched in a single RAS cycle  
>>> using a
>>> page mode access, saving bus time. Needed some tricky arrangement of
>>> the address bits on the DRAM to make this possible. It might have
>>> eliminated the badlines.
>>
>> If you look at it the other way around, without badlines there are  
>> many
>> wasted memory cycles.
>
> Hm? A badline means that the CPU is stopped. If there was no  
> badline it would run and do more or less useful stuff. My  
> assumption was that by using a page mode access to grab data and  
> attributes in one RAS cycle the video logic never needs to halt the  
> CPU.

And then you do three memory accesses per CPU cycle instead of two (call
it 2.6 or whatever if you want to count the lack of second RAS).  Maybe
that's fine with a Z80, but a 6502 can run faster than that :-)

Memory timing and bus timing are more limited than CPU frequency (always
has been, still is, and always for different reasons :-) )

> On the other hand, the ULA in the spectrum used a single hardwired  
> timing, there were no different video modes and no text mode at all  
> (hi-res only!). Maybe it was considered too difficult to make it  
> work on the VIC-II.

The VIC-II was originally designed for SRAM, not DRAM; it was obviously
not considered at all to do tricky things with RAS/CAS timing ;-)


Segher


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