Re: 6500/1 ROM

On Sun, 16 Sep 2012, silverdr@wfmh.org.pl wrote:

> Even if it is so, then few more questions come to mind:
>
> 1. What about the timing? Since I notice no form of handshaking 
> mentioned, I guess one would need to put proper bits on the port 
> according to cycle-exact fetch/execution times?

Unfortunately, the 6500/1 datahsheet is rather thin on details.

Judging from the 6500/11 (not /1) datasheet, I think some pin should 
reflect EMS# (or an OE# signal for external ROM signaling following 
the R65/11 backback emulator description) so that you can detect 
external memory accesses. Otherwise you wouldn't know when the 6500/1 
comes out of initialization but rather need to supply NOPs for at least 
8 cycles after reset goes high, then start feeding in the program.

A further one maybe also R/W# for signaling writes.

Could be checked by wiring Port C to NOP and bringing up the chip in 
external access mode, then probing all pins for undocumented action.

> 2. If it is as you write and [1.] above is solved, then what do I need 
> [to load program into] RAM for? I could supply commands and data until 
> I am done with ROM dump or anything, effectively simulating RAM on the 
> port, couldn't I? I see some contradiction here. Or we understand it 
> wrong.
>
> 3. If I need to load PRG into RAM, how do I switch execution to it 
> when all accesses go to port anyway? Maybe a precisely timed 
> disconnect of the _RES voltage combined with appropriate data 
> preceding it..

To my understanding of the 6500/1 datasheet you now need to put "POKE"s 
on the data lines, i.e. feed in the test program through LDX #$00 and a 
series of LDA #opc / STA $00,X / INX ended by a JMP $0000 and releasing 
the voltage switch.

Following the 6500/11 and 6500/1 memory maps, maybe the first jump below 
the ROM barrier ($F000 with 6500/11, $(F)800 with 6500/1) -- or any 
jump, for that matter -- will release the voltage switch automatically.

Assuming, that the 6500/11 is not completely different from the 6500/1, 
the following datasheet might provide some further food for thoughts 
regarding external memory access and timing:

 	http://www.buchty.net/ensoniq/files/r6500.pdf

Unfortunately, that datasheet doesn't mention anything with regard to 
test logic, but rather features a dedicated backpack emulator.

Regards,
 	Rainer


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