Re: More CPLD explorations

From: silverdr_at_wfmh.org.pl
Date: Tue, 25 Feb 2014 21:44:50 +0100
Message-ID: <etPan.530d00c2.79e2a9e3.45e2@szaman.lan>
On 2014-02-25 at 20:49:07, Gerrit Heitsch (gerrit@laosinh.s.bawue.de) wrote:

> The fun part is, if you look at a chip itself and measure just between 
> +5V and GND of that chip, everything is a bit noisy, but not really  
> bad.
>  
> It's just that the ends of the board in relation to each other do  
> funny
> things. The 1V peak-to-peak is only a few ns, and a half cycle is  
> about 500ns.

Well, this doesn’t mean such thing can be “written off” due to the length of the pulses. Of course it depends on various things but it still can be a disruptive factor for regular operations even if those are short.

> After all, the board is working…

“Barely” as gpz noted ;-) No, kidding - it really depends on “what”, “when” and “where”. Might as well be only a part of the circuit (“where”), which is not critical (“what”) and/or only at times “when” this part is not in use.

--  
SD!

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Received on 2014-02-25 21:00:08

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