Re: CPLDs/FPGAs toolchain

> On 2016-04-22, at 18:52, Jim Brain <brain@jbrain.com> wrote:
> 
> I will tell you what worked for me.  I tried using icarus verilog and other tools to try to learn HDL, but that didn't generate much traction.  So, I switched gears:

This more or less answers :-)

> 	• I picked a vendor (Xilinx, but Altera is also a great choice.  I would probably shy away from Lattice and/or Atmel)

I also considered only the two mentioned but tried not to decide at this stage. IOW tried to avoid "vendor lock" while I have still no idea what I am looking for in those devices. Tried to think of something like a kind of virtual chip that could be programmed and tested in a sim environment.

> 	• I bought a small CPLD trainer board.  They are available for $12.00 (http://ebay.to/1Tnd4dW) on eBay
> 	• I bought a programmer, again from eBay (http://ebay.to/1SyZxj6) for about $26.00
> 	• I downloaded a free tool from the vendor (in this case, Xilinx ISE WebPack, but Altera ha a suitable free solution)
> 	• I bought some of those Arduino "hookup wires"
> 	• I cannibalized a game cart to solder a 44 pin header on the edge connector (not really a game cart, but an old C64 cart PCB I made, though you get the idea)
> 	• I wired IO1, DATA 0-7, R/W, PHI lines between the CPLD and the edge connector
> 	• I dloaded some examples from http://www.asic-world.com/

Great resource it seems. Seems like something exactly for me at my current level :-)

> 	• I created a project in the tool, and figured out how to dload the results to the CPLD
> 	• I wrote some simple code to toggle LEDs on the CPLD board from the 64.
> Lather, rinse, repeat.

Thanks Jim. And thanks to other who answered. Seemingly "vendor lock" is unavoidable if I want to make some progress in this field.

> I will admit that strategic and timely help from a few knowledgeable people who knew more about HDL than I was immensely helpful.  I am happy to pass on that help, because I am now pretty comfortable with the toolchain (Verilog, still learning, as I am still messing up when to use reg or wire)

So you went the Verilog rather than VHDL route, right?

-- 
SD!


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