Den Wed, 18 Oct 2017 21:16:28 +0200 skrev groepaz@gmx.net: > Am Mittwoch, 18. Oktober 2017, 06:00:09 CEST schrieben Sie: > > > El 18 oct 2017, a las 5:45, Jesus Cea <jcea@jcea.es> escribió: > > > > > > The only option I see is that the 6510 is running a tight loop > > > reading commands to read/write those addresses and that the card > > > is releasing the DMA briefly when the fast CPU access those > > > location for the 6510 to continue execution and simulate the > > > access, but this seems complicated and fragile. > > The only other option I see is that when the machine boots, the > > 6510 runs a ROM in the card that copies basic, kernal and chargen > > to the card. After this the card takes control, disable the 6510 > > via DMA and simulates the bank switching internally snooping > > accesses to $0/$1. > > thats exactly what the existing accelerators do. additionally, when > the external CPU writes to its (external) RAM, some DMA mechanism > also writes into the C64s RAM, since the VICII can only "see" the > internal RAM and else you'd get no picture. How does this distinguish between I/O and RAM in the CPU adress space area where I/O overlaps RAM? Are we sure that the 6510 I/O port isn't accessible from external hardware when the CPU is in DMA/three state mode? -- (\_/) Copy the bunny to your mails to help (O.o) him achieve world domination. (> <) Come join the dark side. /_|_\ We have cookies. Message was sent through the cbm-hackers mailing listReceived on 2017-10-19 21:00:03
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