Re: How hardware accelerators deals with $0/$01

Den Wed, 18 Oct 2017 21:12:10 +0200 skrev Spiro Trikaliotis
<ml-cbmhackers@trikaliotis.net>:
> Hello Mia,
> 
> * On Wed, Oct 18, 2017 at 05:09:59PM +0200 Mia Magnusson wrote:
> > Well, since the I/O area (with VIC, SID, 2* CIA) overlaps the
> > character ROM area, the VIC chip can't use that RAM anyway.
> 
> That's not true.

Oh, my memory were incorrect. I though that the char rom would be
visible to the VIC chip in the upper bank, but it isn't.

> But you are right, there is no reason to change the memory map with
> the help of the 6510 on-board I/O port, as it does not affect the VIC
> memory map in any way!
> 
> I think that's what you wanted to tell us, right?

No, as I misremembered it seems like the 6510 I/O port is indeed needed
as there is no other way to select between I/O and the RAM under the
I/O area. That RAM area must be written to for the VIC chip to be able
to use that data.

It would had been far easier to make an accelerator cartridge if there
weren't RAM accessible by VIC and also I/O in the same part of the CPU
adress space.

I'd say that it would be far easier to implement an accelerator as an
internal add-on. That way it could emulate the 6510 I/O port even in
accelerated mode. (Since the 6510 I/O port works like the I/O ports in
6520, 6522, 6526, 6820 e.t.c. it's easy to read it's state in the code
that switches acceleration on/off).

*****:

B.t.w. I've been toying with an idea to make a "super accelerator"
which completely disables on-board ram (with an adapter/replacement for
the PLA) which lets VIC access the faster ram via a buffer. That way
VIC would only have to use one "fast" cycle, i.e. only use one 20MHz
cycle (for a 20MHz 65816) or with fast enough ram it could even use a
"halv cycle" of the 20MHz bus if the RAM is fast enough. That way we
could get rid of the "shadow"/"cache" things in a 65816 accelerator.

I were thinking about not saying anything about this idea and make some
actual hardware and kind of try to surprise the Commodore community.
But knowing myself I'll probably never get around to actually do this,
so I might as well share the idea here. :)

Such hardware could either be a cardridge with some adapter in the PLA
socket, or could be some internal thing sitting in the PLA and CPU
socket. Maybe it would even be better to use a 6502 CPU instead of 6510
for the standard speed mode, as that would use the same $0/$1 emulation
as the accelerated mode, thus getting rid of the need to copy stuff
between emulated and real $0/$1 port. That could also free up some
spare 6510 CPU's if there is any shortage of such CPU's on the
market.

I were kind of thinking about starting with a VIC-20 for something like
this, as I already have two broken VIC-20 CR * that I'm slowly in the
process of repairing. As VIC-20 has an easier bus structure, and as I
anyway want to experiment with adding more memory accessible by the VIC
chip, it would be easy to prepare the machine so I can connect some
accelerator prototype.


* (It seems like someone has connected the power supply to the IEC
  connector on both of them, and one is completely missing a 6522, and
  atleast on one of them the PCB is kind of broken around the 7406
  that's connected to the IEC port as the power from the power supply
  has made that IC so warm that there are melt marks in the underside
  of the case (!)... ).


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