Re: PET 2001 RAM question

Den Tue, 30 Jan 2018 18:08:28 +0100 skrev Gerrit Heitsch
<gerrit@laosinh.s.bawue.de>:
> On 01/30/2018 10:25 AM, Francesco Messineo wrote:
> > Hi all,
> > I'm looking at the 2001 with 2114 RAMs, as always I refer to the
> > schematics found on zimmers.net.
> > One thing that I noticed is that the /WR signal to the 2114 RAMs is
> > qualified with PHI2 (inverted, then N-ANDED with a buffered PHI2),
> > but otherwise all the RAM's chip selects and 244 buffers are only
> > enabled depending on the 6502 address bus and I can't find any PHI2
> > intervention on either the selects or the 244 buffer enabling.
> > So, just for  my ignorance, why the R/W signal from the 6502 needs
> > to be qualified on the right phase of the clock and the address bus
> > doesn't?
> 
> Those are RAMs, they don't care if the address bus changes on the fly 
> during a read cycle. But you don't want that during a write cycle.
> 
> R/W must only go LOW while PHI2 is HIGH. That's what that gate setup
> does.

Addition:

Also as 6502 afaik always drive the adress bus, you anyway need bus
separation between the 6502 and the video circuit, so the video ram
is anyway separate from the main ram. (The same is true for VIC-20, it
has buffers for both the adress and the data bus which is disabled
during the video halv of each cycle).



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