On 02/20/2018 10:49 PM, Mia Magnusson wrote: > > I haven't much experience with DRAMs but from what I've read you'd > really need a 500MHz oscilloscope or similar to be able to really see > all kinds of glitches, so with a more common slower oscilloscope you > are a bit blind. You can see a lot with normal scope since the system clock is only 1 MHz. > Also if there is something suspicious with dram refresh, the ram would > (afaik/iirc) anyway partially get refreshed by normal reads. Basic and > Kernal uses a bunch of addresses <1024 (zero page, stack and other > stuff) which could mean that most but not all of the 128 different > combinations of A0-A6 gets read at some point either in the loops > running while idle or running a basic program and in the interrupt > handlers. The question is, if the 6502 is running a program in ROM, will the logic generate RAS-cycles? If yes, that would provide refresh, if not the DRAM would depend on the refresh counter as long as the CPU is using the ROM. > P.S. Isn't chop mode of an analogue oscilloscope far too slow for this? Depends on the scope... My Hitachi V-1050F will go very high in chop mode. With a DSO you no longer have that problem anyway. Gerrit Message was sent through the cbm-hackers mailing listReceived on 2018-02-21 17:00:10
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