On 22/02/2018 13:47, Michał Pleban wrote: > From a quick look at the schematic, it appears that this signal is used > to determine when it is a good time to issue RDY signal to the CPU. You could fake SYNC by setting it every few clock cycles and then when the refresh circuit tries to stop the CPU you can instead turn off the clock. The registers will likely hold their contents long enough. Message was sent through the cbm-hackers mailing listReceived on 2018-02-22 16:00:09
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