Re: Hardware emulation of 6509 using 6502?

From: Jim Brain <brain_at_jbrain.com>
Date: Sun, 25 Feb 2018 15:51:34 -0600
Message-ID: <b0ee49a4-d78d-9f96-0c24-008cfa38424c@jbrain.com>
On 2/25/2018 3:36 PM, Michał Pleban wrote:
> Hello!
>
> Jim Brain wrote:
>
>> Scope trace shows a delay of ~17nS
> If the clock is at 2 MHz, then half a clock cycle is 250 nS, therefore
> 17 nS is 1/15 th of the cycle, correct?
>
> I can imagine a 32 MHz crystal and a 4-bit counter in the CPLD which is
> synchronized with the incoming PHI2 but generates PHI0 for the 6502
> which is shifted back 1/16 th of cycle.
The incoming PHI0IN of the 6502 needs to be shifted "forward" by 17nS.  
That's tougher than just shifting it back.  I am going to look at PHI1 
inverted and see if I can use that to signal the start of the cycle.

Jim


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Received on 2018-02-25 23:04:13

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