On Sun, Feb 25, 2018 at 03:49:10PM -0600, Jim Brain wrote: > On 2/25/2018 3:33 PM, Francesco Messineo wrote: > >On Sun, Feb 25, 2018 at 10:27 PM, Jim Brain <brain@jbrain.com> wrote: > >>On 2/25/2018 3:24 PM, Jim Brain wrote: > >>> If I look at the 6500 datasheet, I see that the PHI1/PHI2 on the 6502 > >>>trails the incoming PHI0 clock by some amount, but the amount is not > >>>defined > >>>in the datasheet. > >>Scope trace shows a delay of ~17nS > > > >Are you feeding external clock to phi0 input of the 6502? > I am feeding the external PCB PHI2 clock (what normally goes to pin 40 > of the 6509) to PIN2IN (sometimes called PHI0 on some datasheets, but > always on pin 37 of the 6502. > > But, if I look at PHI2 out (pin 39 of the 6502), it is delayed by ~17nS > from the incoming PHI2/PHI0 (pin 37). I think that is the problem. > >If so, I think all should work. > I don't think so. Given the skew, and the fact that the PCB exepcts > that all data will be accessed on the high portion of the 6509 PHI2 > signal, data buffers are probably going tristate about the time the 6502 > (which is 17nS delayed) gets ready to read them. > > It also explains why my LA traces are goofed up. On rising edge of the > 6509 PHI2, the 6502 is still 17nS away from placing the correct data on > the databus, etc. After the rising edge of Phi2 you still have Tmds (the setup time), something like 75ns on a 2MHz part, before the data bus is stable. You're supposed to read the data bus at the *falling* edge of Phi2 (and you have at least 30ns there; Thw, the hold time). Segher Message was sent through the cbm-hackers mailing listReceived on 2018-02-26 00:00:53
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