Jim Brain wrote > I have no idea why I would not see a correct write on that > cycle. Hi, Jim. I'm having trouble following the context here. Is there a reference for the code that's being run, and the cycle you're talking about, please? But I'm guessing the write data on the STA differs because A itself differs, as a result of an earlier /LDA/ which differed. Due to timing, perhaps? I do feel timing is the central issue. Certainly there's a discrepancy from being forced to use the Phi0 input (and thus suffer a slight delay) when an '02 or 'C02 is in use. I agree with MiaM's remarks about the CBM-II clock generation (and BTW: *great* trick for tristating the bus)! Re timing: in line with my last post (about using a flying lead to input a slightly earlier version of the Phi2 signal) I think a suitable tap point on the mobo is pin5 of U57 (the Q of a 74S74). This also attaches to pin 5 and 8 of U41 (a 7428 NOR). I would add a pullup resistor, 1K ohm, say. And fly that signal to the 6502's Phi0 input. I admit this isn't an exact solution but it should be close. By switching to an '02 or 'C02 (and the Phi0 input), we ended up with all the CPU operations happening about one gate-delay later. To compensate, we give the Phi0 input a signal that comes one gate-delay sooner. Keep up the good work, and let us know how you're getting along! -- Jeff -- Sent from: http://cbm-hackers.2304266.n4.nabble.com/ Message was sent through the cbm-hackers mailing listReceived on 2018-02-26 15:00:02
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