On 2/27/2018 11:01 PM, Mia Magnusson wrote: > I'd use an oscilloscope to look at the timing. > > If you have a digital two channel oscilloscope, you could use external > trigger to trig on the R/_W signal and watch the clock and a pin on the > data bus using the two channels. As $06 turns to $96 I'd check D4 and > D7 which is the two signals going from 0 to 1. Well, the second LA shows the data changing very quickly after the write is enabled, and that LA is not bound by a clock signal (it's a free running 16MHz LA). Thus, I am pretty sure the data is changing, not an LA issue. > > I would first make sure that this is a real problem and not just the > logic analyzer showing incorrect data. You might want to add a 74S74 > and hook its set/reset inputs to different outputs of the 74S299 (make > sure you don't load any output too much) and use it's output to > clock/trigger the logic analyzer. This way you get much finer grain. > Adding a dip clip on onto the 74S299 and using really short test leads > to feed the inputs of a 74S74 lets you change the timing without any > soldering or similar. As I don't have either of those ICs (I don't keep S series lying around), my best bet is to route them through a CPLD and try that. But, the design is alreayd messy, so I'd rather think this one out a bit more before just blindly trying things. > IMHO it would probably help to replace Kernal with an eprom emulator > containing test code (or the more tedious way, burning eproms/eeproms > with test code) just to make sure what's really happening, i.e. for > example writing debug data to the I/O ports. Sadly, I do not own a emulator to use, though I can burn flash roms and try them. JIm Message was sent through the cbm-hackers mailing listReceived on 2018-02-28 06:00:25
Archive generated by hypermail 2.2.0.