Re: Hardware emulation of 6509 using 6502?

From: Michał Pleban <*lists_at_michau.name*> Date: Fri, 02 Mar 2018 13:36:41 +0100 Message-ID: <5A994559.1030802@michau.name> · lists_at_michau.name

Hello!

Jim Brain wrote:

> Is there a way to create more debug info on this test, so I can see what
> you expected, and what you received?

Sure, I can do that after the weekend.

> I *assume* it's because the RAM and the CPLD are fighting for the bus
> (to be solved with a board rev), but it would be nice to know.

I think it makes sense. From my cursory look at your Verilog it appears
to me that the RAM is being addressed on every access to the CPU
registers, and to prevent that a pass-through buffer on the data lines
would be required.

Regards,
Michau.

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