Saleae make a nice 16-line logic analyzer if you have a real machine to connect it to. I've looked at the B schematics hundreds of times and I can't follow the timing logic ;-) The rest of the machine is pretty straight forward. Anyway, transcribing the schematics to Kicad is a cool project. Good luck! Steve From: Mia Magnusson <mia@plea.se> To: cbm-hackers@musoftware.de Sent: Tuesday, March 13, 2018 8:11 PM Subject: Re: Hardware emulation of 6509 using 6502? Den Tue, 13 Mar 2018 23:29:38 +0000 (UTC) skrev Steve Gray <sjgray@rogers.com>: > Very intriguing. That plus an internal 1MB ram expansion for the > B-series would make an interesting machine. Steve Or a new machine? :) With 1MB ram, the logic required to both emulate a 6509 and also run a 65816, you have about half a B machine. Might aswell make a completely new machine, compatible with the B machines. I'm (extremely slowly) working on making a copy of the B schematics in KiCad. (That's btw why I sent an update of the KiCad 6509 definition). So far I've drawn the first two pages, with the CPU and all the timing generation circuits. To fully understand how the B works, I think I need some kind of software to make timing diagrams. I don't know if any such software exist, I've actually been tinkering with the idea to use project planning software as the min/max delay time in each gate could be treated as min/max time for a task in a project, and how signals depend on previous delays can be treated like how a task in a project depends on earlier tasks to finish. That would only display one full CPU cycle though, but that is probably no problem. The timing generation on the B is IMHO an example of bad engineering. The basic idea is sound, to divide the 18MHz dot clock by 9 with a shift register wired up as a ring counter and use those outputs to control stuff. However some stuff looks horrible like they use 74*74 flip flops hooked up with one output connected to it's set or reset input to create a short spike on the outputs each time a pulse reaches the clock input. This makes the function really depending on gate times not only being fast enough but also slow enough (!). The P has far less of this stuff as the VIC chip generates a lot of the timing and also as it runs at half the clock frequency compared with the B. -- (\_/) Copy the bunny to your mails to help (O.o) him achieve world domination. (> <) Come join the dark side. /_|_\ We have cookies.Received on 2018-03-14 22:44:56
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