Re: Building a 6502 peripheral - timing

On 03/15/2018 09:21 AM, Baltissen, GJPAA (Ruud) wrote:
> Hallo Patryk,
> 
> 
>> No, it can't. PHI2 is nowhere to connect to there so it has to be taken care of externally.
> 
> I meant: the moment you disable CS, the state of WE doesn't matter anymore. In my designs I always make sure that PHI2 is part of CS selection circuit. Using R/W could be dangerous: what if WE becomes (H) before CS? In that case a bus clash can occur, even it is just a very short time.

In most systems you have bus clashes, but yes, short ones. Someone said 
that this is the reason why a 7501 uses less power than a 8501 (20mA 
less from, what I measured). The 8501 is faster, so it gets its lines 
active before the other side becomes inactive.



> Regarding the use of Intel and Zilog ICs: I always use a 74LS139 to create the needed /RD and /WR signals using PHI2 and R/W as inputs.

A 74LS00 should be able to fulfill the same role with one NAND left over 
for other purposes.

  Gerrit