> On 2018-03-19, at 08:12, afachat@gmx.de wrote: > >>> If r/w goes to read during the cycle, clk suddenly changes and data is >>> latched where it shouldn't. This does not happen on the C64 where the VIC >>> only reads, so no problem here but maybe in other setups. >>> >>> If you need to handle this case you need to delay the rising edge of phi2 >>> (but of course not the falling edge) until address and r/w are stable. >> >> Well, the problem with delays is that I don't know a way to do it in VHDL >> without having additional, faster clock, which I don't have. So I'd need to >> have some form of a buffer and do it externally. > > Well. Depends on what you specify your chip for. If you define it can only be > used in a system where r/w can only change from r to w but not the other way, > you can just use the simple equation for the latch clock combining Phi2, R/W > and select. As I said that works in a C64 too. Obviously I'd like to have it as versatile as possible (but not more ;-) OTOH if that's not feasible, then I rather stick to "first make it work, then optimise" principle. But that's exactly why I am asking those questions and am very thankful for the responses. > As for the hold time of data after phi2 goes low, if noone else drives the bus > at this time, you may be able to get away with the bus capacitance holding the > value. You remember that there are effects in the C64 where you read > "leftover" data from the video access on "open" addresses like I/O? That's > exactly the effect, and here the data has been held even longer, for a full > cycle. It seems like a valid point. Thank you, André. -- SD! - http://e4aws.silverdr.com/Received on 2018-03-19 14:00:03
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