On Fri, Mar 30, 2018 at 10:28 AM, smf <smf@null.net> wrote: > On 29/03/2018 20:44, Nejat Dilek wrote: > >> The difference between that 1-wire protocol and my case is that in >> that protocol at least the master is noise immune. This is not >> possible in my case, whatever address line I choose there will always >> be previously unknown 1/0 toggles because of normal use of the >> computer. > > > The protocol I described will reject invalid data and will restart when > valid data is received. So nothing in the past should make a difference. > > No matter how complex you make the starting mechanism, you should make sure > it can detect that during receipt of a message. > >> Actually it's a good idea to calculate the duration of the line being >> held low or high but in my case it's not possible to continously drive >> this line high or low. > > > Do you have space for a latch? Actually I've already built the prototype pcbs and there is not much space left for a dip ic. http://www.commodore.gen.tr/forum/index.php?action=dlattach;topic=14781.0;attach=23319;image Of course the design can be changed and space could be created using 3 pin smd and gates instead of using 14 pin dip 7408 chip. But I want to experiment this hard situation instead of making it easier :) A bit of masochism :) > > Do you have asynchronous serial on the cpu? It might be a crazy idea, but > you may be able to use the chip select as the serial clock and have the > address line as the data. > Attiny85 has USI, which is SPI if you support it with software I guess. Checking the /OE line in a tight loop and sampling the address line is somewhat a software SPI slave solution actually. Bus on the C64 is practically 2Mhz because of interleaved 6510 and VIC accesses. The questions is: would attiny85 properly cope with clock signals of <500ns. It's worth a try. Then it's a matter of determining the byte boundary of an actual transfer and adapting to it.Received on 2018-03-30 15:00:03
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