On Tue, May 29, 2018 at 6:13 PM, Gerrit Heitsch <gerrit@laosinh.s.bawue.de> wrote: >>>> >>>> hm? >>>> It's a typical design of the era, I've seen several PLLs where a >>>> divider is made with a counter pre-loaded to a specific value and >>>> counting either up or down with one bit being the output. I find also >>>> clever using a half LS74 as a NOT port, since it was free anyway. >>>> What do you consider dirty? >>> >>> >>> >>> Take a look at how it resets. They shorted 'carry out' with 'load' and >>> added >>> a 82pF capacitor to adjust the timing a bit. >> >> >> it "reloads" rather. Anyway, I knew you would point at that but it's >> typical of that era really. >> It works fine, that capacitor just lengthens a bit the reload pulse >> due to asymmetrical sink vs source currents of the LS family. > > > Well, yes, it works... But not really a nice way to do it. so the proper way would be adding a monostable? But then you would delay probably too much also the falling edge of the reload pulse. I don't think they could do better than that easily. > > Also, have you looked at the output of the MC4044? I would have expected > that signal to be less noisy. No, never looked at those signals on a real machine, what matter are the square (or rectangular sometimes) digital signals entering the VIC-II and their correct frequencies (and probably jitter, but I've never actually looked at jitter on those clocks anyway). FReceived on 2018-05-29 19:00:33
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