Am 12. Juni 2018 8:44:49 PM schrieb Jim Brain <brain@jbrain.com>: > On 6/12/2018 12:36 PM, André Fachat wrote: >> >> Wow that reminds me..... >> http://www.6502.org/users/andre/csa/copro/index.html >> Shared control port with optmistic locking :-) > Can you explain the optimistic locking? I see the RAM is dedicated to > one processor for an entire half PHI cycle. Why would locking be needed? The very same port is accessible from both sides, the main CPU and the Copro and controls e.g. the Copro interrupt. The locking works in that if you want to change it, you have to read it first, then write it. If between the read and the write the other side has written to the register, the write fails (is ignored) and that condition can be detected with a BIT operation after the write. Probably a bit of overkill, but you can ensure that the Copro e.g. does not loose interrupts set by the main CPU when it updates the register itself. AndréReceived on 2018-06-12 22:00:04
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