Re: DMA successes with Verilog

(TL;DR in third paragraph, a bit of extra info leads in.)

I looked closely into doubling the DMA transaction rate during PHI2 a long
time ago and learned that RAS timing wasn't variable.  I did work out that
you could change column address within one PHI2 cycle by bumping Ultimax
mode to disable CASRAM out from the PLA momentarily, but not the row
address.  This is due to the c64 wiring RAS directly to the DRAM's and
routing cas through the PLA.

For what its worth, the CAS line routes through the 74ls257's (on
breadbins, that is) to select the A (high address byte) inputs while CAS is
asserted.  This precludes accessing adjacent bytes of memory but does leave
the possibility (however remote) of accessing data on two separate pages
but at the same byte address in one phi2 cycle.

TL;DR -
A RMW operation should be possible without modifying anything but the r/w
signal on the bus according to most FPM datasheets I've studied, but would
require some pretty good timing to ensure the VIC-II has completed its CAS
cycle since the cart has to run blind relative to RAS and CAS.  It's
already capable of counting DOT cycles so that should be easy.

Also, some (very few) early breadbins had 300ns dram's in them.  My
friend's first c64 was a sparkly unit and had 300ns ram's in it.

-David


On Tue, Jun 12, 2018 at 2:31 PM, Jim Brain <brain@jbrain.com> wrote:

>
> On June 12, 2018 at 11:12 AM Mia Magnusson <mia@plea.se> wrote:
>
>
>
> Nice!
>
> Seems like your expansion might be able to have a REU compatible mode
> in the future :)
>
> Long in the future, perhaps.  I suspect that handling all of the
> functionality in an REU will thwart my efforts.
>
> To add content worthy of this group:  Looking at the functionality of the
> REU, I noticed the "swap" functionality, and I wonder if one could perform
> 2 actions in 1 half PHI2 cycle.  I think the DRAM is 200nS or better, and
> maybe with that or with 150nS DRAM, a cart could place the address and set
> R/W to be a read for the first half of the high PHI2 cycle, and then change
> to a write halfway through with new data on the data bus.  That would allow
> a swap to occur in half the time.  I am sure there's some reason why it
> won't work, but it seemed an idea worth considering.
>
> Jim
>
>
>