Re: DMA successes with Verilog

From: silverdr_at_wfmh.org.pl
Date: Thu, 14 Jun 2018 00:07:09 +0200
Message-Id: <57CB81D4-1294-4F46-AB32-5D7B40EB972D@wfmh.org.pl>
> On 2018-06-13, at 19:53, Jim Brain <brain@jbrain.com> wrote:
> 
> implement if the 64 requests the transfer.  The issue, as I understand
> it, is if you want to surreptitiously DMA data into the running 64
> memory map, since you don't know where the 6510 is in it's instruction
> fetch/decode/action cycle, and pulling DMA low will corrupt CPU
> activities in flight.

Roger that. I am about something a litte different though. Something like: the CPU puts some data into a buffer and goes about its other businesses. Once it returns it finds the data processed by a DMA capable circuit that reads the data left by the 6502/6510, processes it and writes back to the same (or another) RAM area. All that without actually stopping the CPU. I heard there were some DMA implementations that worked in such way.

-- 
SD! - http://e4aws.silverdr.com/
Received on 2018-06-14 01:00:04

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