On 6/14/2018 10:18 AM, silverdr@wfmh.org.pl wrote: > Probably yes. It's a matter of wording but to my understanding it's also a form of DMA. Not to discourage folks, but I think you'll get blank stares using the term Direct Memory Access (DMA) to describe what you are wanting. > And I need to get the CPU off the buses, which means tri-state capable buffers for 6502. I simply run the 6502 address and data buffers through '541s or a CPLD. > Or do you have a more clever way of doing this? Well, I can safely say that I can implement your idea on my edv board without using DMA, with a 65c816S on the cart, 512kB of shared RAM, and both CPUs having constant access to the data. Both CPUs can be running at the same time, and even can be operating on the same data (they'd need to provide their own handshaking for simultaneous access to the same byte of data. I just got done doing the same on another platform using 2 63c09 CPUs, each with 512kB of data each that is seen as 1MB of RAM by the main 63c09 CPU on the computer. > Thinking aloud - I wonder if actually dropping the first buffer wouldn't work too. Like instead of putting the data to RAM buffer, putting it directly to the other processor's port would suffice. I think yes. By port, you meant eh general purpose IO port on the 6510/8501? Maybe not. DMA is not needed, as you just store to a specific location in main memory, which maps to a 8 bit latch, and the output of the latch goes to the PIO pins of the second CPU. I doubt you mean that though. > That would mean that the main CPU would be doing its various jobs and occasionally putting the outcome of one of them to the port at the other chip. That other chip would process it and "transparently" (for the main CPU) write the outcome to RAM (or even another device/chip) I am not sure I completely understand your idea, but regardless, I think shared RAM is a better idea. > -- Jim Brain brain@jbrain.com www.jbrain.comReceived on 2018-06-15 05:00:04
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