On 6/14/2018 4:29 PM, Mia Magnusson wrote: > > Why does the badlines work while you supposedly cant DMA any time you > want? (Assuming DMA is synchronised to the clock)? DMA is sync with PHI. Not sure your question, but badlines are when the VIC-II essentially uses the CPU slice of the clock cycle for it's own use. Because it is doing so, it's a badline, and neither the main CPU or any DMA activity can use that slice. > > Anyways if you really want to know what the CPU is doing you could > watch the buses. More than two accesses to concecutive addresses means > that it is fetching from program, i.e. instructions or operands. I don't think that's true. a piece of code that reads data from it's own space would trigger the same rule. > Then > it would be easy to see when it accesses some place else, that must be > data. Backtrace the data bus a bit and then you can be sure where that > instruction started and where it will end. I have faith that if there were easier ways, Gideon would have found and implemented them.Received on 2018-06-15 05:00:17
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