Quoting Julian Perry <jp@digitaltapestries.com>: > Re: Strange 8255 behaviorHello Jeff, > > Sunday, June 17, 2018, 7:36:46 AM, you wrote: > >>>> ON 6/15/2018 9:42 AM, FRANCESCO MESSINEO WROTE: >>>> THAT WOULD BE ACTUALLY ONLY 16 MACROCELLS. ONE OF THE EXAMPLES ON >>>> WINCUPL MAKES 3 X 8 BIT PORTS WITH DDR ON A 32 MACROCELLS CPLD > >> I'M PRETTY SURE I KNOW HOW THIS IS DONE. THE SAME TRICK WAS USED >> FOR I/O IN SOME EARLY INTEL MICROCONTROLLER CHIPS (MCS48 FAMILY). >> I THINK THEY CALLED IT A "QUASI-BIDIRECTIONAL" PORT. > >> WHEN YOU READ THE ADDRESS WHAT YOU GET IS ALWAYS THE STATE OF THE >> ACTUAL PIN (NOT SOME INTERNAL NODE). ALL THE PINS HAVE PULLUP >> RESISTORS. <--- !! > >> THERE IS NO DATA REGISTER. WHEN YOU WRITE TO THE ADDRESS YOU'RE >> WRITING TO THE DDR. ANY BIT THAT'S WRITTEN WITH ZERO BECOMES AN >> OUTPUT, AND THE ONLY POSSIBLE OUTPUT VALUE IS ZERO. THE PIN IS >> ACTIVELY DRIVEN LOW. ANY BIT THAT'S WRITTEN WITH ONE BECOMES AN >> INPUT >> -- AND THE PULLUP RESISTOR BRINGS THE PIN HIGH (UNLESS DRIVEN BY >> EXTERNAL CIRCUITRY). > >> THERE ARE A FEW DRAWBACKS, BUT IT'S A GREAT TRICK! THE PORT USES ONE >> I/O ADDRESS (NOT TWO), AND REQUIRES 8 LATCHES, NOT 16. >> -- JEFF > Doesn't the MOS 6529 work this way? Does it? I don't know. Maybe the idea is used lots of places. I only mentioned Intel because that's where I first heard about it. BTW, this notion of performing output by writing data to the DDR can be handy even with a 6522 or similar (where you *do* have both an Output Register and a DDR). The obvious case is when you want to simulate an open-drain output. But another angle is When you have two different applications which share a single 6522 port. Usually that means you never just write to the port -- instead, to avoid modifying the other app's bits, you're forced to do a read-modify-write every time, which is slower. And that might be important. Example: in 2016 I wrote some bit-bang SPI routines where speed was the top priority. To keep things fast the SPI code would write (not RMW) to the OR. But SPI only "owned" 3 of those bits, so the writes would have zeroes in the other five. These five bits could, without interference, be used as outputs by another application, which would alter the DDR to force them low or let them go high (via pullups). Here [1] is the SPI code, in case anyone's interested. There's another cycle-saving trick which I won't explain here. Jeff http://LaughtonElectronics.com [1] http://forum.6502.org/viewtopic.php?p=45555#p45555 > Julian > > /-- > Best regards, > Julian /mailto:jp@digitaltapestries.comReceived on 2018-06-17 03:00:17
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