Den Sat, 16 Jun 2018 17:36:46 -0400 skrev Jeff Laughton <laughton@cyg.net>: > > >> On 6/15/2018 9:42 AM, Francesco Messineo wrote: > >> that would be actually only 16 macrocells. One of the examples on > >> WinCupl makes 3 x 8 bit ports with DDR on a 32 macrocells CPLD > > I'm pretty sure I know how this is done. The same trick was used > for i/o in some early Intel microcontroller chips (MCS48 family). I > think they called it a "quasi-bidirectional" port. > > When you read the address what you get is always the state of the > actual pin (not some internal node). All the pins have pullup > resistors. <--- !! > > There is no Data Register. When you write to the address you're > writing to the DDR. Any bit that's written with zero becomes an > output, and the only possible output value is zero. The pin is > actively driven low. Any bit that's written with one becomes an > input -- and the pullup resistor brings the pin high (unless driven > by external circuitry). > > There are a few drawbacks, but it's a great trick! The port uses > one i/o address (not two), and requires 8 latches, not 16. It won't work to emulate a 6526 though. At least some of the Intel ports that are made this way actually drives the output high too, but only for a short while, which with the right PCB design is enough to compensate for capacitances in the PCB, improving rise time. -- (\_/) Copy the bunny to your mails to help (O.o) him achieve world domination. (> <) Come join the dark side. /_|_\ We have cookies.Received on 2018-06-17 03:00:30
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